In order to reduce overall testing costs of electronic devices, many systems and/or integrated circuits are fabricated with built-in self-test (BIST) circuits. Such circuits are considered “built-in” as they are formed as part of the system itself, or are included in the substrate of an integrated circuit. A BIST circuit can generate and/or evaluate test signals applied/received to a portion of the integrated circuit or system. BIST capabilities can reduce test times, as the on-board BIST circuits can usually apply or evaluate test signals faster than a standalone tester.
While BIST circuits may test various features of an integrated circuit device, one feature that can benefit from BIST circuits can be interface circuits for transmitting signals between devices or sections of a system. One particular type of interface is the source synchronous parallel interface. A source synchronous parallel interface can transmit data in parallel, and timing for such signals can be based on a transmitting source of the parallel data.
It can be desirable to provide self-testing capabilities for the input and/or output path of an integrated circuit. Such a testing capability can help determine if a data transmission path is introducing errors into data signals. To better understand various aspects of the invention, a BIST approach for a source synchronous parallel interface will now be described. A parallel I/O BIST arrangement is shown in FIG. 5 and designated by the general reference character 500. A test system 500 can include a transmitter section 502 and a receiver section 504. A transmitting section 502 can include functional data inputs lines 506 provided from other portions (e.g. non-test) of a device and a BIST transmitter 508 that generates test data values. Multiplexers 510 can selectively output functional data (func_data[0] to func_data[N]) in a normal (e.g., non-test) mode of operation or BIST test data (test_data[0] to test_data[N]) in a test mode of operation. Data can be transmitted from a transmitter section 502 to a receiver section 504 via parallel link interface 512.
A receiver section 504 can include functional logic 514 that can process functional (non-test) data received from a transmitter section 502, and a BIST receiver 516 that can process test data, and thereby test whether data is being properly transmitted via the interface.
It is desirable for a BIST transmitter 508 and BIST receiver 516 to be capable of detecting common parallel interface type faults including “stuck-at” faults and coupling faults. Stuck-at faults in the parallel link interface 512 can result in a constant output pattern of “1” or “0”. Coupling faults can be caused by a data value on one line adversely affecting that of another line. For example, coupling faults can be tested by the transmission of a pseudo-random bit sequence (PRBS).
FIG. 6 shows a conventional BIST transmitter 608 like that shown as item 508 in FIG. 5, and a conventional BIST receiver 616 like that shown as 516 in FIG. 5.
A conventional BIST transmitter section 608 can include constant bit value source 650, a PRBS generator 652, and select MUXs (654-0 to 654-N). Constant bit value source 650 can provide constant binary values to select MUXs (654-0 to 654-N). PRBS generator 652 can generate a pseudo-random sequence of bit values, in both inverted and non-inverted form, and provide such values to select MUXs (654-0 to 654-N). Each select MUX (654-0 to 655-N) can output one of the constant bit values (0 or 1) or a pseudo-randomly generated bit (or its inverse) according to corresponding pattern select signals (pattern_select—0[0:1] to pattern_select_N[0:1]).
A conventional BIST receiver section 616 can provide a number of tests to detect errors in data transmitted from a BIST transmitter 608. A receiver section 616 can include a PRBS pattern check circuit 656, a constant 0 test circuit 658, a constant 1 test circuit 660, and pass/fail logic 662.
A constant 0 test circuit 658 can test data when all signals transmitted are logic lows (0). Thus, such a circuit can logically OR all such values and flag an error by outputting a high value ZERO_RES. Conversely, a constant 1 test circuit 660 can test data when all signals transmitted are logic highs (1), and thus can logically NAND all such values. If a “0” is detected, an error is present, and test circuit 660 can output a high result value ONE_RES.
A pattern check circuit 656 can check for errors in a PRBS bit sequence. In the conventional example shown, a pattern check circuit 656 can include a PRBS checker (656-0 to 656-N) corresponding to each transmitted data bit. Each PRBS checker (656-0 to 656-N) can provide a result signal (RES[0] to RES[N]) that goes to a logic high in the event a received data value does not match an expected data value. Result signals are logically combined (ORed) in a pattern result circuit 657. Thus, if any bit has an error as determined by PRBS checker (656-0 to 656-N), pattern result circuit 657 will output a high result PRBS_RES.
Results from a constant 0 test circuit 658, a constant 1 test circuit 660, and pattern result circuit 657 can be logically ORed in a pass/fail result circuit 662 to provide an overall test result Pass/Fail Status.
It is almost always desirable to reduce an overall size of an integrated circuit, as reductions in size can translate into lower costs. Accordingly, it would be desirable to arrive at some way of providing a BIST arrangement for a parallel interface that presents a more compact circuit than conventional arrangements, like that of FIG. 6.